Estimating Power for ADSP-2159x/SC59x SHARC+® Processors
●This EE-note describes how to estimate power consumption on ADSP-2159x/SC59x processors, which include SHARC+® high-performance cores and a multitude of peripherals, accelerators, and high-speed Direct Memory Access (DMA) channels. These processors have multiple power and clock domains. This application note provides a simplified methodology for estimating the total System-on-Chip (SoC) power consumption depending on the amount of processor activity.
●Power estimates are based on design simulations and characterization data measured across power supply voltage, core and system clock frequency, and junction temperature (TJ). The power can vary widely depending on how the on-chip ADSP-2159x/SC59x SHARC+® Processor resources are used. Thus, power consumption cannot be estimated accurately without an understanding of the components in use and the usage patterns for those components. By providing the usage parameters, board designers can obtain accurate consumption estimates for developing power supply and thermal relief solutions for their ADSP-2159x/SC59xSHARC+® Processor based products.
●See the following sections of the ADSP-2159x/SC59x SHARC+® Processors datasheet[1] for details specific to discussions throughout this EE-Note:
▲See the Operating conditions section for details regarding supported power supply ranges
▲See the Electrical Characteristics and subsequent Total Internal Power Dissipation sections for details regarding current specifications.
●In the associated file[2] furnished with this EE-note, there is a convenient power calculator tool. This tool allows users to obtain a total power profile by populating the cells in a spreadsheet with data found both in the processor data sheet and calculations specific to the intended application. This document explains the cases related to the information of the power calculator, not mentioned in the data sheet.
●This EE-note also describes how to provide the appropriate input to the power calculator such that the full power profile for the application can be obtained. It describes how the calculations are made and how the results contribute to the overall power profile.
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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April 14,2022 |
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Rev 1 |
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EE-433 |
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468 KB |
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