ADSP-2159x/ADSP-SC591/592/594 SHARC+ Processor Hardware Reference

2021-12-13
●Arm Cortex-A5 Subsystem
■The ADSP-SC591/2/4 processor includes an Arm® Cortex-A5® core. The Arm Cortex-A5 processor is the smallest,lowest cost and lowest power Armv7 application processor. The A5 sub-system in the ADSP-SC591/2/4 processor includes a Floating-Point Unit, NEON Media Processing Engine, Generic Interrupt Controller and a Level 2 Cache Controller. The A5 also includes support for a L1-Cache sub-system and a full-fledged Memory Management Unit.The A5 implements the Armv7 architecture and runs 32-bit Arm instructions, 16-bit and 32-bit Thumb instructions, and 8-bit Java byte-codes in Jazelle state.
■This document describes the Arm Cortex-A5 core and memory architecture used on the ADSP-SC591/2/4 process-or, but does not provide detailed programming information for the Arm processor.
■The applicable documentation for programming the Arm Cortex-A5 processor include:
▲Cortex-A5 Technical Reference Manual, Revision: r0p1
▲Cortex-A Series Programmer's Guide, Revision: r0p1
▲Cortex-A5 NEON Media Processing Engine Technical Reference Manual, Revision: r0p1
▲Cortex-A5 Floating-Point Unit Technical Reference Manual, Revision: r0p1
▲CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual, Revision: r3p3
▲PrimeCell Generic Interrupt Controller (PL390) Technical Reference Manual, Revision: r0p0
●Cortex A5 Features
■The Cortex-A5 subsystem has the following features.
▲Thumb / Arm Instruction support
▲L1- Instruction Cache and L1-Data Cache
▲Floating Point Unit (FPU)
▲NEON Media Processing Engine (NEON)
▲Generic Interrupt Controller (GIC)
▲Level 2 Cache Controller (L2CC)
▲Memory Management Unit (MMU)
●Functional Description
■The following sections provide information on the function of the subsystem.

ADI

ADSP-2159xADSP-SC591ADSP-SC592ADSP-SC59482-100147-01ADSP-21591ADSP-21593ADSP-21594

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Part#

smallest,lowest cost and lowest power Armv7 application processorHARC+ Processor

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Application note & Design Guide

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May 2021

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