ispMACH 4000ZE Family
●Introduction:
■The high performance ispMACH 4000ZE family from Lattice offers an ultra low power CPLD solution. The new family is based on Lattice’s industry-leading ispMACH 4000 architecture. Retaining the best of the previous generation, the ispMACH 4000ZE architecture focuses on significant innovations to combine high performance with low power in a flexible CPLD family. For example, the family’s new Power Guard feature minimizes dynamic power consumption by preventing internal logic toggling due to unnecessary I/O pin activity.
■The ispMACH 4000ZE combines high speed and low power with the flexibility needed for ease of design. With its robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictability, routing, pin-out retention and density migration.
■The ispMACH 4000ZE family offers densities ranging from 32 to 256 macrocells. There are multiple density-I/O combinations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA), and Ultra Chip Scale BGA (ucBGA) packages ranging from 32 to 144 pins/balls. Table 1 shows the macrocell, package and I/O options, along with other key parameters.
■A user programmable internal oscillator and a timer are included in the device for tasks like LED control, keyboard scanner and similar housekeeping type state machines. This feature can be optionally disabled to save power.
■The ispMACH 4000ZE family has enhanced system integration capabilities. It supports a 1.8V supply voltage and 3.3V, 2.5V, 1.8V and 1.5V interface voltages. Additionally, inputs can be safely driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. The ispMACH 4000ZE also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-down and bus-keeper features are controllable on a “per-pin” basis. The ispMACH 4000ZE family members are 1.8V in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary scan testing capability also allows product testing on automated test equipment. The 1532 interface signals TCK, TMS, TDI and TDO are referenced to V-CC (logic core).
●Overview:
■The ispMACH 4000ZE devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which contain multiple I/O cells. This architecture is shown in Figure 1.
■The I/Os in the ispMACH 4000ZE are split into two banks. Each bank has a separate I/O power supply. Inputs can support a variety of standards independent of the chip or bank power supply. Outputs support the standards compatible with the power supply provided to the bank. Support for a variety of standards helps designers implement designs in mixed voltage environments. In addition, 5V tolerant inputs are specified within an I/O bank that is connected to a V-CCO of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI interfaces.
|
ispMACH 4000ZE 、 ispMACH 4032ZE 、 ispMACH 4064ZE 、 ispMACH 4128ZE 、 ispMACH 4256ZE 、 LC4032ZE-4TN48C 、 LC4032ZE-5TN48C 、 LC4032ZE-7TN48C 、 LC4032ZE-4MN64C 、 LC4032ZE-5MN64C 、 LC4032ZE-7MN64C 、 LC4064ZE-4TN48C 、 LC4064ZE-5TN |
|
|
|
|
|
|
|
|
Datasheet |
|
|
|
|
Please see the document for details |
|
|
|
|
|
|
|
|
|
|
|
English Chinese Chinese and English Japanese |
|
|
February 2012 |
|
|
Version 01.7 |
|
|
DS1022_01.7 |
|
|
5.5 MB |
- +1 Like
- Add to Favorites
Recommend
- Why GaN in Space?
- Innoscience Built The First World-class 8-inch Wafer FAB with Gold-free and CMOS Compatible Process
- Two kinds of structure of unit in SiC power MOSFET: plane structure and groove structure
- Successful Demonstration of Next-Gen Ka-band Rx Beamforming IC Portfolio with 1.5dB NF LNA
- Futureway Has Developed a Variety of Silicone Solutions for Battery Pack
- UnitedSiC Rediscovers The Perfect Switch with SiC FETs
- These Kinds of MOS Tubes “Breakdown“, How Many Do You Know?
- Low-Frequency Noise Modeling When Quantum Chips Are Getting Noiser
All reproduced articles on this site are for the purpose of conveying more information and clearly indicate the source. If media or individuals who do not want to be reproduced can contact us, which will be deleted.
Integrated Circuits
Discrete Components
Connectors & Structural Components
Assembly UnitModules & Accessories
Power Supplies & Power Modules
Electronic Materials
Instrumentation & Test Kit
Electrical Tools & Materials
Mechatronics
Processing & Customization
