TOE10GLL-IP reference design
●The general solution for implementing TCP/IP data processor with FPGA is mostly designed by using CPU system for running TCP/IP stack. While the lower layers,link layer and physical layer,can be implemented by Xilinx IP core which is 10/25G Ethernet Subsystem,as shown on the left side of Figure 1-1.Though this solution is flexible for user to design the application on CPU,the result shows much latency time for processing both TCP/IP stack and the application.
●To achieve the lowest latency solution,the design on the right side of Figure 1-1 is designed,the full hardware logic system for processing TCP/IP packet. This solution is fit with the time-sensitive application that needs to implement the user logic by the hardware logic for transferring TCP data with TOE10GLL-IP. TOE10GLL-IP designs TCP/IP stack with ultra-low latency. Also, it is recommended to connect with the low latency 10G Ethernet MAC IP(LL10GEMACIP)to achieve the lowest latency system.The lowest layer of hardware, PMA layer, is provided by Xilinx as a free PMA IP.
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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18-Nov-20 |
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Rev1.0 |
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1.5 MB |
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