TOE10GLL-IP reference design

PublishTime：2021-08-10

●The general solution for implementing TCP/IP data processor with FPGA is mostly designed by using CPU system for running TCP/IP stack. While the lower layers - link layer and physical layer are implemented by Intel IP core, Low Latency Ethernet 10G MAC, as shown on the left side of Figure 1-1. Though this solution is flexible to design application on CPU, the result shows much latency time for processing both TCP/IP stack and the application.
●To achieve the lowest latency solution, the design on the right side of Figure is designed, the full hardware logic system for processing TCP/IP packet. This solution is fit with the time-sensitive application that needs to implement the user logic bythe hardware logic for transferring TCP data with TOE10GLL-IP. TOE10GLL-IP designs TCP/IP stack with ultra-low latency. Also, it is recommended to connect with the low latency 10G Ethernet MAC IP(LL10GEMACIP) to achieve the lowest latency system. The lowest layer of hardware, PMA layer, is provided by Intel as a free PMA IP.

Brand of Product：	Design Gateway
Part#：	TOE10GLL-IP More Part#
Product Category：	More
Application：	More
Data Type：	Application note & Design Guide More
Safety & Environment Standards：	More
Operating Temperature：	Please see the document for details
Qualification Grade：	More
Qualification Approval：	More
Package：
Language：	English Chinese Chinese and English Japanese
Date of Creation：	5-Mav-21
Version Number：	Rev1.1
Data Encoding：
Data Size：	1.5 MB

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