EV8AQ160 Quad ADC
■The Quad ADC is constituted by four 8‐bit ADC cores which can be considered independently (fourchannel mode) or grouped by two cores (two‐channel mode with the ADCs interleaved two by two or one‐channel mode where all four ADCs are all interleaved).
■All four ADCs are clocked by the same external input clock signal and controlled via an SPI (Serial Peripheral Interface). An analog multiplexer (cross‐point switch) is used to select the analog input depending on the mode the Quad ADC is used.
■The clock circuit is common to all four ADCs. This block receives an external 2.5 GHz clock (maximum frequency) and preferably a low jitter symmetrical signal. In this block, the external clock signal is then divided by two in order to generate the internal sampling clocks:
▲In four‐channel mode, the same 1.25 GHz clock is directed to all four ADC cores and T/H
▲In two‐channel mode, the in‐phase 1.25 GHz clock is sent to ADC A or C and the inverted 1.25 GHz clock is sent to ADC B or D, while the analog input is sent to both ADCs, resulting in an interleaved mode with an equivalent sampling frequency of 2.5 Gsps
▲In one‐channel mode, the in‐phase 1.25 GHz clock is sent to ADC A while the inverted 1.25 GHz clock is sent to ADC B, the in‐phase 1.25 GHz clock is delayed by 90° to generate the clock for ADC C and the inverted 1.25 GHz clock is delayed by 90° to generate the clock for ADC D, resulting in an interleaved mode with an equivalent sampling frequency of 5 Gsps
■Several adjustments for the sampling delay and the phase are included in this clock circuit to ensure a proper phase relation between the different clocks generated internally from the 2.5 GHz clock.
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Datasheet |
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Please see the document for details |
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EBGA380 |
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English Chinese Chinese and English Japanese |
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03/16 |
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0846J–BDC;DS0846 |
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3.5 MB |
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