NVMe IP Core for PCIe switch Product Specification

PublishTime：2022-03-25

●General Description
■NVMeSW IP implements as host controller to access NVMe SSD following NVM express standard. Physical interface of NVMe SSD is PCIe. The lower layer hardware is implemented by using Integrated Block for PCI Express from Xilinx.
■NVMeSW IP supports six NVMe commands, i.e. Identify, Shutdown, Write, Read, SMART and Flush command by using two user interface groups. First is Control interface for transferring command and the parameters. Another is Data interface for transferring data when the command must have the data transferring. The Control interface and Data interface for Write/Read command use dgIF typeS format. Control interface of dgIF typeS has start address and transfer length with asserting the request signal while Data interface of dgIF typeS is the FIFO interface.
■Although up to four NVMe SSDs could be connected to NVMeSW IP, only one SSD is operated at a time. NVMeSW IP has the signal for selecting active device, called UserDevSel. The device selection is the input parameter for all commands.
■SMART and Flush command require the specific interface, called Custom command interface, which consists of Ctm I/F for control path and Ctm RAM I/F for data path. Furthermore, Identify command has its own data interface, named Iden RAM I/F, as shown in Figure 2.
■During initialization or running some commands, error signal may be asserted by NVMeSW IP if some abnormal conditions are found. The IP includes the error status to check the more details of error condition. To recover error status, NVMeSW IP and all SSDs must be reset.
■There is one limitation about clock frequency of user logic. Transmit packet to PCIe hard IP must be sent continuously until end of packet. Therefore, data must be valid every clock between start of packet and end of packet. To support this feature, user logic clock frequency must be more than or equal to PCIe clock frequency (250 MHz for PCIe Gen3) to have the bandwidth of transmit logic higher than or equal to PCIe hard IP bandwidth.
■The reference design on FPGA evaluation boards are available to evaluate before purchasing.
●Features
■NVMe host controller for access one NVMe SSD by direct connection or up to four NVMe SSDs by connection through one PCIe switch
■No need for CPU and external memory
■Include 256 Kbyte RAM to be data buffer
■Simple user interface by dgIF typeS to access one device at a time
■Support six commands, i.e. Identify, Shutdown, Write, Read, SMART, and Flush
■Supported NVMe device
▲Base Class Code:01h (mass storage), Sub Class Code:08h (Non-volatile), Programming Interface:02h (NVMHCI)
▲MPSMIN (Memory Page Size Minimum): 0 (4Kbyte)
▲MDTS (Maximum Data Transfer Size): At least 5 (128 Kbyte) or 0 (no limitation)
▲LBA unit: 512 bytes or 4096 bytes
■User clock frequency must be more than or equal to PCIe clock (250 MHz for PCIe Gen3)
■Operating with Integraged Block for PCI Express from Xilinx by using 4-lane PCIe Gen3 (128-bit bus interface)
■Available reference design: KCU105, ZCU106 and VCU118 with AB18-PCIeX16/AB16-PCIeXOVR adaptor board
■Customized service for following features
▲Additional NVMe commands
▲RAM size or RAM type (URAM) modification
▲Support more than four NVMe SSDs

Brand of Product：	Design Gateway
Part#：	XCKU040FFVA1156-2E 、 XCZU7EV-FFVC1156-2E 、 XCVU9P-FLGA2104-2L More Part#
Product Category：	NVMe IP Core More
Application：	[ PCIe switch ][ NVMe SSD ][ FIFO ] More
Data Type：	Datasheet More
Safety & Environment Standards：	More
Operating Temperature：	Please see the document for details
Qualification Grade：	More
Qualification Approval：	More
Package：
Language：	English Chinese Chinese and English Japanese
Date of Creation：	October 12, 2020
Version Number：	Rev1.2
Data Encoding：
Data Size：	1.6 MB

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