NVMe-IP reference design manual

PublishTime：2022-03-17

● NVM Express (NVMe) defines the interface for the host controller to access solid state drive (SSD) by PCI Express. NVM Express optimizes the process to issue command and completion by using only two registers (Command issue and Command completion). Also, NVMe supports parallel operation by supporting up to 64K commands within single queue. 64K command entries improve transfer performance for both sequential and random access.
● In PCIe SSD market, two standards are used AHCI and NVMe. AHCI is the older standard to provide the interface for SATA hard disk drive while NVMe is optimized for non-volatile memory like SSD. The comparison between AHCI and NVMe protocol in more details is described in “A Comparison of NVMe and AHCI” document.
● To access NVMe SSD, the general system implements NVM e driver running on the processor, as shown in the left side of Figure 1-1. The physical connection of NVMe standard is PCIe connector which is one to one type, so one PCIe host connects to one PCIe device without usings witch NVMe IP implements NVMe driver to access NVMe SSD by using pure hardware logic. The user can access NVMe SSD without including any processor and driver but using NVMe IP in FPGA board. Using pure hardware logic for NVMe host controller reduces the overhead time for software hardware handshake, so NVMe IP can show very high performance for writing and reading with NVMe SSD.

Brand of Product：	Design Gateway
Part#：	NVMe-IP More Part#
Product Category：	More
Application：	More
Data Type：	Application note & Design Guide More
Safety & Environment Standards：	More
Operating Temperature：	Please see the document for details
Qualification Grade：	More
Qualification Approval：	More
Package：
Language：	English Chinese Chinese and English Japanese
Date of Creation：	7-Jun-21
Version Number：	Rev 3.7
Data Encoding：
Data Size：	862 KB

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