NVMe-IP reference design manual
■NVM Express (NVMe) defines the interface for the host controller to access solid state drive (SSD) by PCI Express. NVM Express optimizes the process to issue command and completion by using only two registers (Command issue and Command completion). Also, NVMe supports parallel operation by supporting up to 64K commands within single queue. 64K command entries improve transfer performance for both sequential and random access.
■In PCIe SSD market, two standards are used - AHCI and NVMe. AHCI is the older standard to provide the interface for SATA hard disk drive while NVMe is optimized for non-volatile memory like SSD. The comparison between AHCI and NVMe protocoI in more details is described in “A Comparison of NVMe and AHCI” document.
■https://sataJo.og/svstem/filesAnennber-downloads/N\/Me%20and%20AHCI %20 lonq .pdf
■The example of NVMe storage device is shown in http:"www.nvmexpress.orq/products/.
■To access NVMe SSD, the general system implements NVMe driver running on the processor, as shown in the left side of Figure H. The physical connection of NVMe standard is PCIe connector which is one-to-one type, so one PCIe host connects to one PCIe device without using switch. NVMe-IP implements NVMe driver to access NVMe SSD by using pure-hardware logic. The user can access NVMe SSD without including any processor and driver but using NVMe IP in FPGA board. Using pure-hardware logic for NVMe host controller reduces the overhead time for software-hardware handshake, so NVMe-IP can show very high performance for writing and reading with NVMe SSD.
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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5-Mar-21 |
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Rev3.6 |
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830 KB |
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