FPGA-IPUG-02066-1.2 SEDC Module - Lattice Radiant Software User Guide
■This document provides technical information about the SEDC (Single Error Detect/Correct Module ) that is supported in Lattice FPGA devices built on the Lattice Nexus™ platform. This aims to provide information essential for IP/System developers, Verification and Software for integration, testing and validation. In general, design specification from RTL up to IP packaging, IP generation, and integration with Lattice Radiant® software are covered in this document.
▲Supports both SEC (Single Error Correct) and SED (Single Error Detect) modes
▲Output information on Soft Error location
▲Supports SEC without the need for external memory access
▲Support for SEI (Soft Error Injector) tool
▲Including support to target errors to a specific block of logic
▲Flexible handling of SEC events -> Freeze I/O, GSR, and others
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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June 2021 |
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FPGA-IPUG-02066-1.2 |
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908 KB |
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