FPGA-IPUG-02071-1.3 I²C Master IP Core - Lattice Radiant Software User Guide
■The I²C (Inter-Integrated Circuit) bus is a simple, low-bandwidth, short-distance protocol. It is often seen in systems with peripheral devices that are accessed intermittently. It is commonly used in short-distance systems, where the number of traces on the board should be minimized. The device that initiates the transmission on the I²C bus is commonly known as the Master, while the device being addressed is called the Slave.
■Lattice Semiconductor general-purpose I²C Master IP Core offers an effective way to control an I²C bus. The programmable nature of FPGA provides you with flexibility of configuring the I²C Master device to their needs, thus allowing you to customize the I²C Master Controller to meet their specific design requirements.
●Features:
■The key features of l²C Master IP Core include:
▲Supports 7-bit and 10-bit Addressing Mode
▲Programmable SCL frequency, supporting the following bus speeds:
▲Standard-mode (Sm) - up to 100 kbit/s
▲Fast-mode (Fm) - up to 400 kbit/s
▲Fast-mode Plus (Fm+) - up to 1 Mbit/s
▲Integrated Pull-up
▲Integrated Glitch filter
▲Arbitration lost detection in multi-master system
▲Polling and Out-of-band Interrupt Modes
▲Selectable LMMI or APB interface supports Clock stretching
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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June 2021 |
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FPGA-IPUG-02071-1.3 |
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1.1 MB |
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