FPGA-IPUG-02072-1.3 I²C Slave IP Core - Lattice Radiant Software User Guide
■I²C (Inter-Integrated Circuit) bus is a simple, low-bandwidth, short-distance protocol. It is often seen in systems with peripheral devices that are accessed intermittently. It is commonly used in short-distance systems, where the number of traces on the board should be minimized. The device that initiates the transmission on the l2C bus is commonly known as the Master, while the device being addressed is called the Slave.
■Lattice Semiconductor general-purpose l²C Slave IP Core provides device addressing, read/write operation and an acknowledgement mechanism. The programmable nature of FPGA provides users with the flexibility of configuring the l²C Slave device to any legal Slave address, thus, avoiding a potential Slave address collision on an l²C bus with multiple Slave devices.
●Features:
■The key features of l2C Slave IP Core include:
▲Supports 7-bit and 10-bit Addressing Mode
▲Supports the following bus speeds:
▲Standard-mode (Sm) - up to 100 kbit/s
▲Fast-mode (Fm) - up to 400 kbit/s
▲Fast-mode Plus (Fm+) - up to 1 Mbit/s
▲Supports Clock stretching
▲Configurable ACK/NACK response on address and data phases
▲Integrated Pull-up
▲Integrated Glitch filter
▲Polling and Out-of-band Interrupt Modes
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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June 2021 |
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FPGA-IPUG-02072-1.3 |
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1.2 MB |
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