PT7C4512 PLL Clock Multiplier
■This Clock Multiplier is the most cost-effective way to generate a high quality, high frequency clock outputs from lower frequency crystal or clock input. It is designed to replace crystal oscillators in most electronic systems, clock multipliers and frequency translation devices with low output jitter. The device implements a standard fundamental mode using PLL techniques and inexpensive crystal to produce output clocks up to 200 MHz.The internal Logic divider is to generate nine different popular multiplication factors, allowing one chip to output many common frequencies.
●Features
■Zero ppm multiplication error
■Input crystal frequency of 5 - 40 MHz
■Input clock frequency of 4 - 50 MHz
■Output clock frequencies up to 200 MHz
■Low period jitter 80ps (100~200MHz)
■Duty cycle of 45/55% of output clock up to 160MHz
■9 selectable frequencies controlled by S0, S1 pins
■Operating voltages of 3.0 to 5.5V
■Lead free SOIC-8 package
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Datasheet |
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Please see the document for details |
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SOIC-8;8-SOIC (W);SOIC |
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English Chinese Chinese and English Japanese |
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February 2018 |
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Rev 2-2 |
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DS40692 |
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488 KB |
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