UDP1G-IP Core

PublishTime：2021-08-10

●Features
■UDP/IP stack implementation
■Support IPv4 protocol
■Full-duplex transferring by using two port numbers for each transfer direction
■Support more sessions by using multiple UDP1G-IPS
■Various Transmit/Receive buffer size (2 KB. 4KB, 8KB. 16KB, 32KB. and 64KB)
■Simple data interface by standard FIFO interface
■Simple control interface by single port RAM interface
■8-bit Avalon stream to interface with Tnple-Speed Ethernet MAC from Intel
■User clock frequency fixed to 125 MHz clock frequency
■Reference design available on CycloneVE/ArriaV
GX/Cyclone 10GX/Arria 10 SoC/Arria10 GX
Development Board
■Support IP fragmentation
▲Customized service for following features
▲Multicast IP
▲Network parameter assignment by other methods

Brand of Product：	Design Gateway
Part#：	5CEFA7F31I7 、 5AGXFB3H4F35C5 、 10GX220YF780E5G 、 10AS066N3F40E2SGE2 、 UDP1G More Part#
Product Category：	IP Core More
Application：	More
Data Type：	Datasheet More
Safety & Environment Standards：	More
Operating Temperature：	Please see the document for details
Qualification Grade：	More
Qualification Approval：	More
Package：
Language：	English Chinese Chinese and English Japanese
Date of Creation：	March 26.2021
Version Number：	Rev1.5
Data Encoding：
Data Size：	738 KB

Data section preview(2pages)

- The full preview is over. If you want to read the whole 21 page document,please Sign in/Register -

Download

+1 Like
Add to Favorites

Recommend

Technical Resources

More>

All reproduced articles on this site are for the purpose of conveying more information and clearly indicate the source. If media or individuals who do not want to be reproduced can contact us, which will be deleted.

Integrated Circuits