USB3.0 (Host) IP Protocol & Link Layer Core Product Specification
■The USB3.0 (Host) IP Core implements link layer and protocol layer. Only setting data address on memory prepared by Host processor, transmission length and other parameter to the register in the IP Core, IP Core will process dividing into packets, adding CRC & Scramble and flow control on USB bus, and return processing result to the register. Data receive process is also same flow.
■Host interface of the IP Core consist of simple register access interface, provide simple DMA access interface for memory and able to connect to NiosII or uniphy_ddr3.
■For connection with PHY chip, it is compliant with standard PIPE interface. So it is just able to connect through Flip-Flop for timing adjustment with FPGA port.
■Internal clock in the IP Core is more than 125MHz (125M x 4bytes = 500MB/s) and clock for connection with PHY chip is fixed to 250MHz (500MHz x 2 bytes). However Host interface and DMA interface are able to connect by low frequency clock using necessary synchronization.
●Features
■Compliant with the USB 3.0 specification revision 1.0
■Support SuperSpeed (5Gbps)
■USB3.0 Host Contoroller
■Imprement link layer and protocol layer
■Physical layer interfaces to PHY chip by TI (TUSB1310A)
■IP core clocks are adjustable (250MHz for PIPE I/F, more than 125MHz for internal)
■Support 16bit PIPE interface
■Support IN/OUT root point up to 15 points
▲1 point for control
▲7 points each for IN/OUT
■Support All transmission taps (Control, Bulk, Isochronous and Interruput transmission)
■Simple transaction interface with Host processor or DMA interface
■Free demo SOF file for evaluation on Altera board.
■Reference design available on CycloneIV GX, CycloneVE, ArriaV GX Development Kit with Design GateWay AB08-USB3HSMC Card
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EP4CGX150DF31C7 、 EP2AGX125EF35C4 、 5CEFA7F31I7 、 5AGXFB3H4F35C4 |
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Datasheet |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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3 June 2015 |
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Rev 1.4E |
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305 KB |
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