ESD Ratings of UnitedSiC FETs and JFETs Application Note
■This Application Note discusses the ESD capabilities of UnitedSiC's transistor offerings.
●ESD rating of SiC FETs
■UnitedSiC's FET product line is built on the core technology of a High-Voltage, Normally-On SiC JFET coupled with a Low Voltage, Normally-Off Silicon MOSFET in a cascode configuration. Given the cascode configuration of the SiC JFET and Si MOSFET, the MOSFET is connected to the Gate and Source pins of a package, and it the limiting device when itcomes to ESD capability. The JFETs are p-n junctions and can handle far more ESD than the MOSFET. Our MOSFETs use integrated diodes as ESD protection, and the size and capacitance of the MOSFET become the determining factorin ESD capability.
●ESD Rating of SiC JFETs
■Similar to the MOSFETs, the UnitedSiC family of SiC JFETs are scaled with size and the smallest devices are the most sensitive to ESD. Unlike the MOSFETs, the JFET is fundamentally insensitive to ESD because the device is made up of p-n junctions. Utilizing the smallest JFET in the lineup, Charged Device Model testing was done to ±1000V, and Human Body Model testing for all pin pairs was done to ±8000V. Putting all JFETs in the C3 and H3A classes, respectively.
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transistor 、 SiC FETs 、 JFETs |
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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March 2021 |
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AN0027 |
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669 KB |
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