Empowering Innovation, Cologne Chip FPGA Solution: Ideal for Seamless Integration in Projects of Every Scale, from small to High-Volume Applications

PublishTime： 2024-02-20 Article Source：Cologne Chip

The GateMate^TM FPGA family of Cologne Chip AG addresses all application requirements of small to medium size FPGAs. Logic capacity, power consumption, package size, and PCB compatibility are best in class. GateMate^TM FPGAs combine these features with the lowest cost in industry making the devices well-suited from University projects to high volume applications. Because of the outstanding circuit size/cost ratio, new applications now can use the benefits of FPGAs.

All this is based on a novel FPGA architecture combining CPE programmable elements with a smart routing engine. The CPE architecture allows an efficient building of arbitrarily-sized multipliers. Memory aware applications can use block RAMs with bit widths of 1 to 80 bits.

General Purpose IOs (GPIOs) can use different voltage levels from 1.2 to 2.5Volts. All GPIOs can be configured as single-ended or LVDS differential pairs. Furthermore, a high-speed SerDes interface is available.

FPGA designs are synthesized using the Yosys framework. The free Cologne Chip P&R-software generates the FPGA bitstream.

A Static Timing Analysis (STA) is also performed and gives evidence about critical paths and the overall performance of a design. The design can be simulated using Verilog netlist and SDF timing extraction.

The devices are manufactured using the Globalfoundries^TM 28 nm SLP (Super Low Power) process. Due to manufacturing in Europe, there is no danger of trade restrictions or high taxation.

GateMate^TM FPGA Overview

The GateMate A1 FPGA is the smallest-dimensioned component of the GateMate^TM Series. With its 20,480 logic elements, it is ideally suited for lowest-power applications.

GateMate^TM FPGA Features

Novel CPE Architecture

20,480 programmable elements (CPE) for combinatorial and sequential logic

40,960 Latches / Flip-Flops within programmable elements

CPE consists of LUT-tree with 8 inputs

Each CPE is configurable as a 2-bit full-adder or 2x2-bit multiplier

Low Power Consumption

Globalfoundries^TM 28 nm SLP (Super Low Power) process

3 operation modes: low power, economy, speed

No excessive start-up currents

Only two supply voltages are needed and can be applied in any order

Features

4 programmable PLLs

Fast configuration with quad SPI interface up to 100 MHz

Multi-Chip configuration

1,280 Kbit dual ported block RAM with variable data widths in 32 x 40 Kbit RAM cells

Multipliers with arbitrary size implementable in CPE array

Multiple clocking schemas

All 162 GPIOs are configurable as single-ended or LVDS differential pairs

Double data rate (DDR) support in all GPIO cells

5 Gb/s SerDes

Package

324-ball BGA package (15x15mm)

Only 2 signal layers are required on the PCB

GateMate^TM FPGA Starter Kit
The GateMate^TM FPGA Starter Kit is the perfect starting point for all embedded designers exploring a flexible and low-power platform, based on the latest Cologne Chip technology and targeted at cost-sensitive designs.

The Starter Kit consists of all required hardware components for evaluating and developing a wide range of applications and includes:

Evaluation Board with GateMate A1 FPGA

Programmer Adapter and flat ribbon cable for your PCB

USB cable

GateMate^TM FPGA Series: Feature Summary by Device
The Cologne Chip GateMate^TM family addresses a complete range of system requirements. The following table compares all available devices:

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