For the 5V40501 PLL clock multiplier, is it possible to change the divide constant dynamically by manipulating the S0 and S1 lines, or must these lines remain stable from power-up?
- 创建于2020-05-06
1answer(s)
-
- (0)
- Yes, the S0 and S1 can be changed to manipulate the clock divider.
- Published:2020-05-06
- +1 Like
- Add to Favorites
Recommend
More>
- Benefits of a Point-of-Use Clock for Jitter Optimization Back to top
- CHX2193-FAA, a 6.25-8.25GHz Internally Matched Frequency Multiplier in a 6×6mm Hermetic Ceramic Package
- Second-Generation of ClockMatrix Family of Network Synchronizers and Jitter Attenuators for Optical and Wireline Networks
- Renesas’ New Programmable Clock Generator Delivers Industry’s Best Combination of Programmability, Power, Jitter, and Size
- A Registering Clock Driver Used on DDR5 RDIMMs and LRDIMMs——Renesas RCD 5RCD0148HC2
- 3 Reasons Why Using SiC Diodes in Your High Voltage Multiplier
- Epson’s Low Jitter Programmable SPXO SG-8200/01CG with Low Noise Fractional-N PLL Technology Ideal for Various Applications
- AEC-Q100 Qualified Clock Generator Adopted on NXP S32G Automotive Network Processor Reference Design