PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide
●About the PHY Lite for Parallel Interfaces IP
■This user guide describes the following IPs:
▲PHY Lite for Parallel Interfaces Agilex™ 5 FPGA IP (E-Series)
▲PHY Lite for Parallel Interfaces Agilex 7 FPGA IP (M-Series)
▲PHY Lite for Parallel Interfaces Agilex 7 FPGA IP (F-Series and I-Series)
▲PHY Lite for Parallel Interfaces Stratix® 10 FPGA IP
▲PHY Lite for Parallel Interfaces Arria® 10 FPGA IP
▲PHY Lite for Parallel Interfaces Cyclone® 10 GX FPGA IP
■You can primarily use the PHY Lite for Parallel Interfaces IPs for building custom memory interface PHY blocks. You can use this solution to interface with protocols such as DDR2, LPDDR2, LPDDR, TCAM, Flash, ONFI (synchronous mode), and mobile DDR. The PHY Lite for Parallel Interfaces Intel® FPGA IP is suitable for simple parallel interfaces.
■The IPs have a dedicated PHY clock tree in each I/O bank. The PHY clock tree is short that yields lower jitter and duty cycle distortion (DCD), enabling designs to achieve higher performance. This IP controls the strobe-based capture I/O elements. Each instance of the IP can support interfaces of data/strobe capture groups.
■In addition, this IP supports the Dynamic Reconfiguration feature, which enables reconfiguration of the data and strobe delays. You can align the data and strobe through calibration to achieve timing closure at high frequencies.
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Agilex 5 、 E-Series 、 Agilex 7 、 F-Series 、 I-Series 、 M-Series 、 Stratix 10 、 Arria 10 、 Cyclone 10 GX |
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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2024.04.01 |
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6.2 MB |
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