MIPI D-PHY IP User Guide Agilex™ 5 FPGAs
●Introduction
■Agilex 5 devices offer native mobile industry processor interface (MIPI) D-PHY for both D-series and E-series devices.
■This support complies to MIPI D-PHY version 2.5, and allows transmission or reception of data with MIPI D-PHY interfaces. It provides the PHY-protocol interface (PPI) to connect with camera serial interface (CSI) and display serial interface (DSI) applications.
■The Agilex 5 MIPI D-PHY feature supports high-speed (HS) and low-power (LP) modes and allows direct interface with the D-PHY compliance component without external components. The Agilex 5 MIPI D-PHY can perform up to 3.5Gbps for D-Series and E- Series device group A and up to 2.5Gbps for E-Series device group B for high-speed (HS) mode for data traffic, and up to 20MHz for low-power (LP) mode for control traffic. Each HSIO bank can support up to a maximum of 7 interfaces. The supported data lanes per-interface are 1, 2, 4 or 8, with one clock lane. The D-PHY lanes support only unidirectional operation. The MIPI D-PHY IP provides an AXI-Lite interface for register access.
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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2024.07.08 |
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1.9 MB |
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