LVDS SERDES User Guide Agilex™ 5 FPGAs and SoCs
●Agilex™ 5 LVDS SERDES Overview
■The Agilex™ 5 I/O system includes four types of I/O interfaces—high-speed I/O (HSIO), high-voltage I/O (HVIO), Secure Device Manager (SDM) I/O, and Hard Processor System (HPS) I/O. Each I/O interface caters to different interfacing requirements.
■Agilex 5 devices support LVDS serializer/deserializer (SERDES) through the True Differential Signaling I/Os in the HSIO banks. The true differential I/Os are capable of supporting LVDS interfaces, including subsets such as:
▲RSDS
▲Mini-LVDS
▲SLVS
▲Any I/O standards using equivalent electrical specifications
■Agilex 5 devices support SERDES in all HSIO banks with the following features:
▲Configurable transmitter or receiver on all I/O pins
▲Serialize and deserialize functions up to 1.6 Gbps.
▲Clock data recovery (CDR) function on specific differential channel
▲Configurable 100 Ω differential on-chip termination (OCT RD)
▲Serialize or deserialize factors of 4 and 8(1)
▲I/O standards support for the LVDS SERDES:
◆Transmitter—True Differential Signaling I/O standard at 1.3 V
◆Receiver:
★DPA mode—True Differential Signaling and SLVS-400 I/O standards
★Non-DPA mode—True Differential Signaling I/O standard only
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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2024.07.08 |
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1.2 MB |
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