Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs
●Agilex™ 5 Configuration Overview
■All Agilex™ 5 FPGAs and SoCs are devices that include a Secure Device Manager (SDM) to manage FPGA configuration and security. The SDM provides a failsafe, strongly authenticated, programmable security mode for device configuration. Previous FPGA families include a fixed state machine to manage device configuration.
■The Quartus® Prime software also provides flexible and robust security features to protect sensitive data, intellectual property, and the device itself under both remote and physical attacks. Configuration bitstream authentication ensures that the firmware and configuration bitstream are from a trusted source. Encryption prevents theft of intellectual property. The Quartus Prime software also compresses FPGA bitstreams, reducing memory utilization such as the on-board quad SPI flash device that is storing the FPGA bitstreams.
■Intel describes configuration schemes from the point of view of the FPGA. Agilex 5 devices support active and passive configuration schemes. In active configuration schemes the FPGA acts as the master and the external memory acts as a slave device. In passive configuration schemes an external host acts as the master and controls configuration. The FPGA acts as the slave device. All Agilex 5 configuration schemes support design security and partial reconfiguration. All Agilex 5 active configuration schemes support remote system update (RSU) with quad SPI flash memory. To implement RSU in passive configuration schemes, an external controller must store and drive the configuration bitstream.
■Agilex 5 devices support the following configuration schemes:
▲Avalon® streaming (Avalon-ST)
▲JTAG
▲Configuration via Protocol (CvP)
▲Active Serial (AS) normal and fast modes
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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2024.07.08 |
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3.2 MB |
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