MPC107 Revision 1.3 and 1.4: Comparison and Compatibility

2022-04-26
This document describes electrical and functional differences between Rev 1.3 and Rev 1.4 of the MPC107 PCI Bridge/Memory Controller, which provides a bridge between the Peripheral Component Interconnect (PCI) bus and the MPC603e, MPC740, MPC750, MPC745, MPC755, MPC7400 and MPC7410 PowerPC™ host processors.
For a few years now, the production revision of the MPC107 has been Rev 1.3. However, this version of the device is limited to a processor/memory bus frequency of 100 MHz and has errata that some customers have deemed unsuitable for their design requirements. Recently a new revision of the MPC107, Rev 1.4, was introduced to implement fixes for the errata to make it more suitable for new designs. Specification changes that manufacturing supports also addressed the frequency limitation. Because many existing designs are unaffected by the 100-MHz limit and the errata on Rev 1.3, and because Rev 1.4 introduces timing and functional changes to the 107, many customers choose to continue specifying Rev 1.3 in their designs. This document, which describes the differences between Rev 1.3 and Rev 1.4,provides help to assess which revision is appropriate for a specific design and what changes might be necessary when migrating a system design from Rev 1.3 to Rev 1.4.

NXP

MPC107MPC603eMPC740MPC750MPC745MPC755MPC7400MPC7410MPC7450 familyMPC7450

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PCI Bridge/Memory Controllerhost processors

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Application note & Design Guide

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2006/1/25

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