Designing PCI 2.1-Compliant MPC106 Systems

PublishTime：2022-04-26

Some PCI target devices are not compliant with specifications found in the PCI Local Bus Specification (Revision 2.1). This application note describes how to use the MPC106 to create well-designed PCI-based systems. The user should be familiar with the MPC106,the PCI Local Bus Specification, board layout, and routing concepts. The MPC106 PCI Bridge/Memory Controller provides a bridge between the Peripheral Component Interconnect(PCI) bus and Freescale's MPC603e, MPC740, MPC750, MPC745, MPC755, MPC7400 and MPC7410 PowerPC™ host processors.
The MPC106 has a single clock input (SYSCLK) that is used to clock the PCI interface.The PCI interface of the system must run in phase with this input. The PCI 2.1 specification allows the system designer to have flexibility of PCB layout so that all components on the PCI bus must have their PCI clocks routed within 2.0 ns of each other.This point, combined with the PCI 2.1 specification shown in Figure 1, which states that 0 ns input hold time is required, results in systems where the output hold requirement is 2.0 ns.

Brand of Product：	NXP
Part#：	MPC603e 、 MPC740 、 MPC750 、 MPC745 、 MPC755 、 MPC7400 、 MPC7410 、 MPC106 More Part#
Product Category：	PCI Bridge/Memory Controller 、 host processors More
Application：	More
Data Type：	Application note & Design Guide More
Safety & Environment Standards：	More
Operating Temperature：	Please see the document for details
Qualification Grade：	More
Qualification Approval：	More
Package：
Language：	English Chinese Chinese and English Japanese
Date of Creation：	6/2003
Version Number：	Rev. 0.1
Data Encoding：	AN1727/D
Data Size：	360 KB

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