Initializing SDRAM Parameters for Motorola MPC106-Based Systems

PublishTime：2022-04-26

This document describes the correlation of the programmable SDRAM interface parameters of Motorola's MPC106 PCI bridge/memory controller and typical SDRAM parameters found in manufacturers' data sheets. The MPC106 PCI bridge/memory controller provides a PowerPC™ microprocessor common hardware reference platform (CHRP™) compliant bridge between the PowerPC microprocessor family and the Peripheral Component Interconnect (PCI) bus.
Additional information about the topics discussed in this document can be found in MPC106 PCI Bridge/Memory Controller User's Manual (order #: MPC106UM/AD), and Addendum to MPC106 PCI Bridge/Memory Controller User's Manual: MPC106 Revision 4.0 Supplement and User's Manual Errata (order #: MPC106UMAD/AD). In this document, the term '106' is used as an abbreviation for, 'MPC106 PCI bridge/memory controller'.
To locate any published errata or updates for this document.
Note that this document describes the parameters for Rev. 4.0 of the MPC106. Earlier revisions are slightly different, but the information presented here is applicable with minor adjustment. For example, Rev. 4.0 has a 10-bit BSTOPRE parameter while Rev. 3.0 has an 8-bit BSTOPRE parameter. This means that while Rev. 4.0 devices can have a burst-to-precharge interval of 1023 clock cycles, Rev 3.0 devices are restricted to an interval of 255 clock cycles.

Brand of Product：	NXP
Part#：	MPC106 More Part#
Product Category：	PCI bridge/memory controller More
Application：	More
Data Type：	Application note & Design Guide More
Safety & Environment Standards：	More
Operating Temperature：	Please see the document for details
Qualification Grade：	More
Qualification Approval：	More
Package：
Language：	English Chinese Chinese and English Japanese
Date of Creation：	6/2003
Version Number：	Rev. 0.1
Data Encoding：
Data Size：	343 KB

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