Initializing SDRAM Parameters for Motorola MPC106-Based Systems
Additional information about the topics discussed in this document can be found in MPC106 PCI Bridge/Memory Controller User's Manual (order #: MPC106UM/AD), and Addendum to MPC106 PCI Bridge/Memory Controller User's Manual: MPC106 Revision 4.0 Supplement and User's Manual Errata (order #: MPC106UMAD/AD). In this document, the term '106' is used as an abbreviation for, 'MPC106 PCI bridge/memory controller'.
To locate any published errata or updates for this document.
Note that this document describes the parameters for Rev. 4.0 of the MPC106. Earlier revisions are slightly different, but the information presented here is applicable with minor adjustment. For example, Rev. 4.0 has a 10-bit BSTOPRE parameter while Rev. 3.0 has an 8-bit BSTOPRE parameter. This means that while Rev. 4.0 devices can have a burst-to-precharge interval of 1023 clock cycles, Rev 3.0 devices are restricted to an interval of 255 clock cycles.
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Application note & Design Guide |
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Please see the document for details |
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