EVDK Based Speed Sign Detection Demonstration
● This document provides technical information and instructions for setting up and running the EVDK Based Speed Limit Sign Detection Demo. This demo is designed to utilize the Lattice Machine Learning Engine (MLE) IP and implemented onto the Lattice Embedded Vision Development Kit (EVDK). The EVDK Based Speed Limit Sign Detection Demo performs the speed limit sign detection using the camera on the EVDK and feeds the video stream through the Convolutional Neural Network (CNN) inside Lattice MLE. The detected speed limit sign is reported through the HDMI output. The CNN in the Lattice MLE is trained with actual speed limit signs.
● Refer to the following documents for detailed information on Lattice development boards and kit:
▲ Lattice Embedded Vision Development Kit User Guide (FPGA-UG-02015)
▲ CrossLink VIP Input Bridge Board Evaluation Board User Guide (FPGA-EB-02002)
▲ ECP5 VIP Processor Board Evaluation Board User Guide (FPGA-EB-02001)
▲ HDMI VIP Output Bridge Board Evaluation Board User Guide (FPGA-EB-02003)
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LF-EVDK1-EVN 、 ML-EVN-ADP 、 MICROSD-ADP-EVN 、 LFE5UM-25F 、 LPE5UM-25F 、 LAE5UM-25F 、 LFE5UM-45F 、 LAE5UM-45F 、 LFE5UM-85F 、 LAE5UM-85F 、 ECP5UM 、 ECP5UM Family 、 SPI-N25Q128A 、 MX25L12835F 、 LIF-MD6000 、 LIA-MD6000 、 LIFMD Family 、 LIFMD 、 SPI-M25PX16 、 SPI-MT25QL128A |
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User's Guide |
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Please see the document for details |
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SO8;WSON;S08W;SOP2 |
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English Chinese Chinese and English Japanese |
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June 2021 |
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Revision 1.2 |
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FPGA-UG-02049-1.2 |
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1.5 MB |
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