LogiCORE IP Multiply Accumulator v3.0 DS716
●Introduction: The Xilinx® LogiCORE™ IP Multiply Accumulator core provides implementations of multiply-accumulate using DSP slices. It accepts two operands, a multiplier and a multiplicand, and produces a product (A*B=Prod) that is added/subtracted to the previous result (S=S+/-Prod). This product value can be loaded by asserting Bypass (S=Prod). The function can be pipelined. The Multiply Accumulator module operates on signed or unsigned data.
●Features
■Supports twos complement-signed and unsigned operations
■Supports multiplier inputs ranging from 1 to 31 bits unsigned or 2 to 32 bits signed and an output width ranging from 1 to 79 bits unsigned or 2 to 80 bits signed
■Optional clock enable and synchronous clear
■Latency can be set for optimal speed or minimal pipelining
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LogiCORE IP Multiply Accumulator 、 IP Multiply Accumulator core |
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Datasheet |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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October 2, 2013 |
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v3.0 |
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DS716 |
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687 KB |
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