LogiCORE IP Multiplier v11.2 Product Specification DS255
●Introduction
▼The Xilinx LogiCORE™ IP Multiplier implements high-performance,optimized multipliers.A number of resource and performance trade-off options are available to tailor the core to a particular application.
●Features
▼Drop-in module for Virtex®-7 and Kintex™-7, Virtex-6,Virtex-5,Virtex-4,Spartan®-6， Spartan-3/XA,Spartan-3E/XA, Spartan-3A/3AN/3A DSP/XA FPGAs
▼Generates fixed-point parallel multipliers and constant-coefficient multipliers for two's complement signed or unsigned data
▼Supports inputs ranging from 1 to 64 bits wide and outputs ranging from 1 to 128 bits wide with any portion of the full product selectable
▼Configurable latency for all multiplier variants
▼Resource estimation in the Xilinx CORE Generator™ graphical user interface(GUD)
▼Supports symmetric rounding to infinity for Virtex and Kintex device multipliers when using the XtremeDSP™ slice
▼For use with Xilinx CORE Generator and Xilinx System Generator for DSP 13.1
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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March 1, 2011 |
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v11.2 |
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DS255 |
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501 KB |
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