LogiCORE IP SPI-4.2 Lite v5.2
★Introduction
▼The Xilinx LogiCORE™ IP SPI-4.2 (PL4)Lite core implements,and is functionally compliant with,the OIF-SP14-02.1 System Packet Interface Phase 2 standard. This fully verified solution interconnects physical layer devices to link layer devices in 2.5 Gbps POS,A™,and Ethernet applications.
★Features
▼Up to 275+ MHz DDR on SPI-4.2 interface supporting 550 Mbps pin pair total bandwidth
▼Supports Static Phase Alignment
▼Bandwidth optimized Source core achieves optimal bus throughput without additional FPGA A resources
▼Flexible pin assignment:maximum core performance achievable with user defined pinouts
▼Configurable 32-bit or 64-bit user interface
▼Multiple core support-more than 4 cores can be implemented in a single device
▼Sink and Source cores configured through Xilinx CORE Generator™ software for easy customization
▼Delivers Sink and Source cores as independent solutions,enabling flexible implementation
▼Supports 1-256 addressable channels with fully configurable SPI-4.2 calendar interface
▼Supports LVTTL or LVDS Status FIFO path operating at 1/4 or 1/8 of the data rate
▼Provides DIP-4 and DIP-2 parity generation and verification
▼Provides Sink and Source FIFO controls for flushing the contents of the FIFO without restarting the interface
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Datasheet |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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April 19, 2010 |
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v5.2 |
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DS502 |
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1.1 MB |
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