DS717 LogiCORE IP Multiply Adder v3.0
●Introduction: The Xilinx® LogiCORE™ IP Multiply Adder core provides implementations of multiply-add using DSP slices. It performs a multiplication of two operands and adds (or subtracts) the full-precision product to a third operand. The Multiply Adder module operates on signed or unsigned data. The module can be pipelined.
●Features
■Supports twos complement-signed and unsigned operations
■Supports multiplier inputs ranging from 1 to 52 bits unsigned or 2 to 53 bits signed and an add or subtract operand input ranging from 1 to 105 bits unsigned or 2 to 106 bits signed
■Optional clock enable and synchronous clear
■Optional pipelined operation
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LogiCORE IP Multiply Adder 、 LogiCORE™ IP Multiply Adder core |
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Datasheet |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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April 02, 2014 |
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v3.0 |
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DS717 |
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349 KB |
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