SMART CXL Memory Module, Which is Compatible with PCIe-Gen5 Speeds Running At 32GT/s

PublishTime： 2022-02-15 Article Source：SMART

Compute Express Link (CXL) is an open industry interconnect standard for providing high bandwidth and low latency. It adds connectivity between host processors, accelerators, memory devices, and network interface cards (NICs). CXL also enables memory expansion and acceleration across high-performance computational workloads for AI, ML, HPC, and communications segments. CXL uses PCIe Gen 5.0 PHY based high-speed serial link to communicate between the latest generation of CPU processors.

SMART develops CXL Type 3 (CXL.mem) memory products to address the industry’s need for more memory per processor core. The CXL interconnect specification allows for a significant expansion of memory form factor options leveraged from SSDs. SMART’s introductory CXL Memory Modules known as XMM are offered in the E3.S form factor.

Why choose SMART Modular for CXL?

• SMART is a contributing member of the CXL consortium, closely collaborating with CPU and silicon suppliers to test for compatibility and feature completeness.

• SMART has PCB design and assembly to develop high speed memory and storage modules in variety of form-factors like DIMMs, E1.S, E3.S and PCIe add-in cards.

• SMART’s global manufacturing footprint and strong relationships with components suppliers minimizes disruption even in stringent supply-chain conditions.

• Customers can leverage SMART’s test and validation service for pre-screening memory modules for reliability and quality. • SMART’s engagement in other emerging technologies like Gen-Z, OpenCAPI and persistent memory solutions such as NVDIMM-N.

Key Features

• CXL-2.0 compatible with PCIe-Gen5 speeds running at 32GT/s

• Available in 64GB DDR5 memory capacity with expansion up to 256GB in future

• Supports Reliability, Availability and Serviceability (RAS) features added in CXL-2.0

• Available in EDSFF E3.S 2T (2U short) form-factor.

• Powered by only 12V supply from EDSFF compatible edge interface (SFF-TA-1009)

• Supports sideband interfaces for real-time debug, management and system update, enabling out-of-band management of the module

• Supports additional security features to protect data from sidechannel attacks

• Total Memory = 3TB (DDR5) + 2TB (CXL) per server

• Theoretical maximum bandwidth of 768GB/s (DDR5)+ 252GB/s CXL XMMs

• Bandwidth per core = 5.3GB/s (higher even with more CPU cores)

Applications

• Disaggregated pool of shared memory for HPC applications accessible over CXL fabric

• Secure memory for managing trusted keys and in-memory database

• OLTP Log Cache Acceleration

• In-line compression, encryption or vector atomic operations, transparent to CPU while using normal memory load/store semantics

• Targeted for 2U servers to enables memory expansion with up to 16 E3.S modules in single 2U server achieving better throughput than direct attached DDR5 DIMMs.

Ordering Information

+1 Like
Add to Favorites

Recommend

Technical Resources

More>

New Products & Solutions

More>

This document is provided by Sekorm Platform for VIP exclusive service. The copyright is owned by Sekorm. Without authorization, any medias, websites or individual are not allowed to reprint. When authorizing the reprint, the link of www.sekorm.com must be indicated.

Integrated Circuits