Ceramic Leadless Chip Carrier Packages (CLCC)
◆NOTES:
■Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals.
■Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.)
■Symbol "N" is the maximum number of terminals. Symbols "ND" and "NE" are the number of terminals along the sides of length "D" and "E", respectively.
■The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected.
■The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the drawing.
■Chip carriers shall be constructed of a minimum of two ceramic layers.
■Dimension "A" controls the overall package thickness. The maxi-mum "A" dimension is package height before being solder dipped.
■Dimensioning and tolerancing per ANSI Y14.5M-1982.
■Controlling dimension: INCH.
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Outline Dimension Drawing |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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7/08 |
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Rev. 1 |
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95 KB |
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