ZL30117 SONET/SDH Low Jitter Line Card Synchronizer Data Sheet
◆Features
★Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813
★Internal APLL provides standard output clock frequencies from 6.48 MHz up to 622.08 MHz with jitter less than 1 ps RMS for OC-48/STM-16 interfaces
★Programmable output synthesizer generates clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz
★Digital Phase Locked-Loop(DPLL)provides all the features necessary for generating SONET/SDH compliant clocks including automatic hitless reference switching,automatic mode selection (locked,free-run,holdover),and selectable loop bandwidth
★Provides 3 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz
★Provides 3 sync inputs for output frame pulse alignment
★Generates several styles of output frame pulses with selectable pulse width,polarity,and frequency
★Configurable input to output delay,and output to output phase alignment
★Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities
★Supports IEEE 1149.1 JTAG Boundary Scan
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[ MicroTCA Systems ][ Multi-Service Edge Switches ][ Routers ][ DSLAM Line Cards ][ VAN Line Cards ][ RNC ][ Mobile Switching Center Line Cards ][ ADM Line Cards ] |
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Datasheet |
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Please see the document for details |
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64 Pin CABGA;64 Pin CABGA* |
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English Chinese Chinese and English Japanese |
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February 2006 |
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631 KB |
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