ZL30108 SONET/SDH Network Interface DPLL Data Sheet
★Description
◆The ZL30108 SONET/SDH network interface digital phase-locked loop (DPLL)provides t timing and synchronization for SONET/SDH network interface cards.
◆The ZL30108 generates a SONET/SDH clock and framing signals that are phase locked to one of two backplane or network references.It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining tight phase alignment between the input reference clock and clock outputs.
◆The ZL30108 output clock's wander and jitter generation are compliant with GR-253-CORE OC-3 and G.813 STM-1 specifications.
★Features
◆Supports output wander and jitter generation specifications for GR-253-CORE OC-3 and G.813 STM-1 SONET/SDH interfaces
◆Accepts two input references and synchronizes to any combination of 2 kHz,8 kHz,1.544 MHz. 2.048MHz,8.192Hz,16.384 MHz or19.44MHz inputs
◆Provides a 19.44 MHz(SONET/SDH)clock output
◆Provides an 8 kHz framing pulse and a 2 kHz multi-frame pulse
◆Provides automatic entry into Holdover and return from Holdover
◆Hitless reference switching between any combination of valid input reference frequencies
◆Provides lock and accurate reference fail indication
◆Loop filter bandwidth of 29 Hz or 14 Hz
◆Less than 24 psrms intrinsic jitter on the 19.44 MHz output clock,compliant with GR-253-CORE OC-3 and G.813 STM-1 specifications
◆Less than 0.5 nspp intrinsic jitter on output frame pulses
◆External master clock source:clock oscillator or crystal
◆Simple hardware control interface
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Please see the document for details |
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32 Pin QFN;32 Pin QFN* |
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English Chinese Chinese and English Japanese |
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May 2009 |
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1.5 MB |
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