P9027LP-R-EVK Layout Guide Application Note AN-933
Using the Reference Layout: The P9027LP-R-EVK reference layout is a full feature four-layer design optimized for high-performance, small-size, and ease-of-use. The purpose is to minimizedesign-in effort and risk by providing a proven solution that can be imported into an existing system design. The P9027LP-R-EV board layout can be divided into two parts;the main function layout (core layout) and the layout for test purpose. When imported into an existing system, only the core layout is necessary. The core layout follows the design rules for wearable devices with minimum space and trace width of 4 mils. The minimum finished VIA size is 4 mils, assuming 1 mil plating thickness. The minimumspacing between components is 0.2mm. Only through hole VIAs are used. There are no blind or buried VIAs. When circumstances permit, it is highly recommended to copy the reference layout.
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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May 16, 2016 |
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AN-933 |
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1.1 MB |
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