AS4C1G16D4
■The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as an eight-bank DRAM for the x16 configuration.
■The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins.
■A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
●Features
■VDD = VDDQ = 1.2V ±60mV
■VPP = 2.5V, –125mV, +250mV
■On-die, internal, adjustable VREFDQ generation
■1.2V pseudo open-drain I/O
■Refresh time of 8192-cycle at TC temperature range:
▲64ms, at –40℃ to 85℃
▲32ms, at >85℃ to 95℃
■8 internal banks (x16): 2 groups of 4 banks each
■8n-bit prefetch architecture
■Programmable data strobe preambles
■Data strobe preamble training
■Command/Address latency (CAL)
■Multipurpose register READ and WRITE capability
■Write leveling
■Self refresh mode
■Low-power auto self refresh (LPASR)
■Temperature controlled refresh (TCR)
■Fine granularity refresh
■Self refresh abort
■Maximum power saving
■Output driver calibration
■Nominal, park, and dynamic on-die termination (ODT)
■Data bus inversion (DBI) for data bus
■Command/Address (CA) parity
■Databus write cyclic redundancy check (CRC)
■Per-DRAM addressability
■Connectivity test
■JEDEC JESD-79-4 compliant
■sPPR and hPPR capability
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Datasheet |
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Please see the document for details |
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FBGA |
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English Chinese Chinese and English Japanese |
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August 2024 |
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Rev 2.0 |
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20.5 MB |
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