Introduction to Compute Express Link (CXL®) Memory Modules White Paper
■Compute Express Links (CXL®) is a high-speed interconnect standard that enables an efficient link between the CPU and platform subsystems. It builds upon PCI Express® infrastructure, leveraging the PCIe® 5.0 physical and electrical interfaces. CXL encourages heterogeneous and distributed compute architecture by enabling hardware based cachecoherency for all types of compute engines like CPU, GPU, and accelerators xPUs (TPU, DPU, IPU, etc.).
■The biggest advantage of CXL comes with the extension of the memory attachment to serial interface. This fills the gap for data-intensive applications as they drive the requirements for high bandwidth and provide low-latency and sharing across multiple devices in a system. Serializing the memory interface also opens up opportunities for connecting memory in different form-factors like Add-in-Cards (AIC) and EDSFF modules, which simplifies system design, and lowers the TCO by allowing memory modules to be mechanically and electrically compatible to SSDs.
■The CXL standard specifies three protocols:
▲CXL.io: CXL.io is functionally equivalent to the PCIe interface. This sub-protocol is used for configuration, DMA and Interrupt handling between device and Host.
▲CXL.mem: CXL.mem enables a host, such as a processor, to access the device-attached memory using load/store commands.
▲CXL.cache: CXL.cache specifies semantics and rules for accelerators trying to access directly attached memory connected to the CPU’s DDR bus. This enables accelerators to efficiently access and cache host memory for optimized performance.
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Please see the document for details |
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Rev.5 |
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