AS4C1G8D4A 1024M x 8 bit DDR4 Synchronous DRAM (SDRAM)
■JEDEC Standard Compliant
■Fast clock rate: 1600MHz
■Power supplies:
▲VDD & VDDQ = +1.2V ± 0.06V
▲VPP = +2.5V -0.125V / +0.25V
■Operating temperature:
▲Industrial : TC = -40~95°C
▲Commercial : TC = 0~95°C
■Supports JEDEC clock jitter specification
■Bidirectional differential data strobe, DQS &DQS#
■Differential Clock, CK & CK#
■16 internal banks: 4 groups of 4 banks each
■Separated IO gating structures by Bank Group
■8n-bit prefetch architecture
■Precharge & Active power down
■Auto Refresh and Self Refresh
■Low-power auto self refresh (LPASR)
■Self Refresh Abort
■Fine Granularity Refresh
■Dynamic ODT (RTT_PARK & RTT_Nom & RTT_WR)
■Write Leveling
■DQ Training via MPR
■Programmable preamble is supported both of 1tCK and 2tCK mode
■Command/Address (CA) Parity
■Data bus write cyclic redundancy check (CRC)
■Internal VREFDQ Training
■Read Preamble Training
■Control Gear Down Mode
■Per DRAM Addressability (PDA)
■Output Driver Impedance Control
■Dynamic on-die termination (ODT)
■Input Data Mask (DM) and Data Bus Inversion (DBI)
■ZQ Calibration
■Command/Address latency (CAL)
■Maximum Power Saving Mode (MPSM)
■Asynchronous Reset
■DLL enable/disable
■Burst Length (BL8/BC4/BC4 or 8 on the fly)
■Burst type: Sequential / Interleave
■CAS Latency (CL)
■CAS Write Latency (CWL)
■Additive Latency (AL): 0, CL-1, CL-2
■Average refresh period
▲8192 cycles/64ms (7.8us at -40°C ≤ TC ≤ +85°C)
▲8192 cycles/32ms (3.9us at +85°C ≤ TC ≤ +95°C)
■Data Interface: Pseudo Open Drain (POD)
■RoHS compliant
■Hard post package repair (hPPR)
■Soft post package repair (sPPR)
■Package: Pb Free and Halogen Free
▲78-ball 7.5 x 12 x 1.2mm FBGA
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AS4C1G8D4A 、 AS4C1G8D4A-62BCN 、 AS4C1G8D4A-62BIN 、 AS4C1G8D4A-62BC/INXX |
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Datasheet |
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Please see the document for details |
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FBGA |
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English Chinese Chinese and English Japanese |
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July 2023 |
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Rev 1.0 |
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11.6 MB |
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