AS4C1G8D4 AS4C512M16D4 DDR4 SDRAM

PublishTime：2020-10-16

The DDR4 SDRAM is a high-speed dynamic random-access memory internally conured as sixteen-banks, 4 bank group with 4 banks for each bank group for x4/x8 and eight-banks, 2 bank group with 4 banks for each bankgroup for x16 DRAM. The DDR4 SDRAM uses a 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.
Read and write operation to the DDR4 SDRAM are burst oriented, start at a selected location, and continue for a burst length of eight or a'chopped’ burst of four in a programmed sequence. Operation begins with the registration of an ACTIVATE Command, which is then followed by a Read or Write command. The address bits registered coincident with the ACTIVATE Command are used to select the bank and row to be activated (BG0-BG1 in x4/8 and BG0 in x16 select the bankgroup;BA0-BA1 select the bank; A0-A15 select the row; The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst operation, determine if the auto precharge command is to be issued (via A10), and select BC4 or BL8 mode'on the fly' (via A12) if enabled in the mode register.
Prior to normal operation, the DDR4 SDRAM must be powered up and initialized in a predefined manner. The following sections provide detailed information covering device reset and initialization, register definition, command descriptions, and device operation
Features:
-1.2V pseudo open-drain interface
-8n prefetch architecture-Internal VREFDQ training
-Programmable data strobe preambles
-Data strobe preamble training
-Command/Address latency (CAL)
-Multipurpose register READ and WRITE capability
-Write and read leveling
-Auto refresh and self refresh Modes
-Low-power auto self refresh (LPASR)
-Auto Self Refresh (ASR) by DRAM built-in TS
-Fine granularity refresh-Self refresh abort
-Maximum power saving
-Output driver calibration
-Configurable on-die termination (ODT)
-Data bus inversion (DBI) for data bus
-Command/Address (CA) parity
-Databus write cyclic redundancy check (CRC)
-Per-DRAM addressability
-Connectivity test (x16)

Brand of Product：	Alliance
Part#：	AS4C1G8D4 、 AS4C512M16D4 、 AS4C1G8D4-75BCN 、 AS4C1G8D4-75BIN 、 AS4C512M16D4-75BCN 、 AS4C512M16D4-75BIN 、 AS4C512M16D4/1G8D4-75BC/INXX More Part#
Product Category：	DDR4 SDRAM More
Application：	More
Data Type：	Datasheet More
Safety & Environment Standards：	More
Operating Temperature：	Please see the document for details
Qualification Grade：	More
Qualification Approval：	More
Package：	FBGA
Language：	English Chinese Chinese and English Japanese
Date of Creation：	Aug 2020
Version Number：	Rev 1.0
Data Encoding：
Data Size：	8.5 MB

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