AS4C1G8D4 AS4C512M16D4 8Gb DDR4 - FBGA PACKAGE Datasheet
■Density: 8G bits
■Organization:
▲64M words x 8 bits x 16 banks (AS4C1G8D4)
▲64M words x 16 bits x 8 banks (AS4C512M16D4)
■Package:
▲78-ball FBGA for x8 / 96-ball FBGA for x16
▲Lead-free (RoHS compliant) and Halogen-free
■Power supply:
▲VDD, VDDQ = 1.2V ± 60mV
▲VPP = 2.5V, -125mV / +250mV
■Data rate: 2133Mbps/2400Mbps/2666Mbps
■1KB page size for X8 / 2KB page size for X16
▲Row address: A0 to A15
▲Column address: A0 to A9
■Sixteen-banks (4 bank group with 4 banks for each bank group) for x8 and eight-banks (2 bank group with 4 banks for each bank group) for x16
■Burst lengths (BL): BL8, BC4, BC4 or 8 on the fly
■Burst type (BT): Sequential, Interleave
■CAS Latency (CL): 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21
■CAS Write Latency (CWL): 9, 10, 11, 12, 14, 16, 18
■Additive Latency (AL): 0, CL-1, CL-2
■CS to Command Address Latency (AL): 3, 4, 5, 6, 8
■Command Address Parity Latency: 4, 5, 6
■Write Recovery time: 10, 12, 14, 16, 18, 20, 24
■Driver strength: RZQ/7, RZQ/5 (RZQ = 240 Ω)
■RTT_PARK (34/40/48/60/80/120/240)
■RTT_NOM (34/40/48/60/80/120/240)
■RTT_WR (80/120/240)
■Read Preamble (1T/2T)
■Write Preamble (1T/2T)
■LPASR (Manual: Normal/Reduced/Extended, Auto: TS)
■Refresh cycles (Average refresh period):
▲7.8 μs at -40°C ≤ Tc ≤ +85°C
▲3.9 μs at +85°C < Tc ≤ +95°C
■Operating case temperature range
▲Commercial Tc = 0°C to +95°C
▲Industrial Tc = -40°C to +95°
●Features
■1.2V pseudo open-drain interface
■8n prefetch architecture
■Internal VREFDQ training
■Programmable data strobe preambles
■Data strobe preamble training
■Command/Address latency (CAL)
■Multipurpose register READ and WRITE capability
■Write and read leveling
■Auto refresh and self refresh Modes
■Low-power auto self refresh (LPASR)
■Auto Self Refresh (ASR) by DRAM built-in TS
■Fine granularity refresh
■Self refresh abort
■Maximum power saving
■Output driver calibration
■Configurable on-die termination (ODT)
■Data bus inversion (DBI) for data bus
■Command/Address (CA) parity
■Databus write cyclic redundancy check (CRC)
■Per-DRAM addressability
■Connectivity test (x16)
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AS4C1G8D4 、 AS4C512M16D4 、 AS4C1G8D4-75BCN 、 AS4C1G8D4-75BIN 、 AS4C512M16D4-75BCN 、 AS4C512M16D4-75BIN 、 AS4C512M16D4-75BCNXX 、 AS4C1G8D4-75BCNXX 、 AS4C512M16D4-75BINXX 、 AS4C1G8D4-75BINXX |
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8Gb DDR4 、 DDR4 SDRAM 、 high-speed dynamic random-access memory |
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Datasheet |
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Please see the document for details |
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FBGA |
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English Chinese Chinese and English Japanese |
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Dec 2021 |
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Rev.1.1 |
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8.4 MB |
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