AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Revision History 1Gb SDRAM-AS4C64M16D1A - 66pin TSOP II PACKAGE
data rate synchronous DRAM containing 1024 Mbits. It is
internally configured as a quad 16M x 16 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CK).
Data outputs occur at both rising edges of CK and CK. Read
and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed
sequence. Accesses begin with the registration of a
BankActivate command which is then followed by a Read or
Write command. The device provides programmable Read
or Write burst lengths of 2, 4, or 8. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst sequence.
The refresh functions, either Auto or Self Refresh are easy to
use. In addition, 1Gb DDR features programmable DLL
option. By having a programmable mode register and
extended mode register, the system can choose the most
suitable modes to maximize its performance. These devices
are well suited for applications requiring high memory
bandwidth; result in a device particularly well suited to high
performance main memory and graphics applications.
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[ applications requiring high memory bandwidth ][ high performance main memory and graphics applications ] |
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Datasheet |
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Halogen Free 、 Pb Free |
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Please see the document for details |
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Commercial 、 Industrial |
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English Chinese Chinese and English Japanese |
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Oct.2015 |
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Rev. 1.0 |
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2.7 MB |
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