Xilinx Answer 72702 UltraScaleand UltraScale+ PCIe Interrupt debug guide
■This document provides the steps involved to initiate Legacy, MSI and MSI-x interrupts with different IP cores targeting UltraScale and UltraScale+ devices.(Xilinx Answer 58495) provides the theoretical background and the steps to initiate Legacy and MSI interrupts with the 7 Series Integrated block IP core.
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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09/20/2020 |
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72702 |
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1.3 MB |
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