UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs
■Chapter 2: Board and Device Planning: Covers decisions and design tasks that Xilinx recommends accomplishing prior to design creation. These include I/O and clock planning, PCB layout considerations, device capacity and throughput assessment, alternate device definition, power estimation, and debugging.
■Chapter 3: Design Creation with RTL: Covers the best practices for RTL definition and IP configuration and management.
■Chapter 4: Design Constraints: Provides recommendations for creating proper timing, power, and physical constraints as well as specifying additional constraints, attributes, and other elements used during synthesis and implementation.
■Chapter 5: Design Implementation: Covers the options available and best practices for synthesizing and implementing the design.
■Chapter 6: Design Closure: Covers the various design analysis and implementation techniques used to close timing on the design or to reduce power consumption. It also includes considerations for adding debug logic to the design for hardware verification purposes.
●This guide includes references to other documents such as the Vivado Design Suite User Guides, Vivado Design Suite Tutorials, and Quick-Take Video Tutorials. This guide is not a replacement for those documents. Xilinx still recommends referring to those documents for detailed information, including descriptions of tool use and design methodology.
●This information is designed for use with the Vivado Design Suite, but you can use most of the conceptual information with the ISE® Design Suite as well.
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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February 18, 2021 |
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v2020.2 |
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UG949 |
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12.6 MB |
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