ProcessorPM-POWR605
●Description:
■Lattice’s Power Manager II ProcessorPM-POWR605 is a general-purpose power-supply monitor, reset genera-tor and watchdog timer, incorporating both in-system programmable logic and analog functions implemented in non-volatile E²CMOS® technology. The Proces-sorPM-POWR605 device provides six independent ana-log input channels to monitor power supply voltages. Two general-purpose digital inputs are also provided for miscellaneous control functions.
■The ProcessorPM-POWR605 provides up to five open drain digital outputs that can be used for controlling DC-DC converters, low-drop-out regulators (LDOs) and opt-ocouplers, as well as for supervisory and general-pur-pose logic interface functions. The five digital, open drain outputs can optionally be configured as digital inputs to sense more input signals as needed, such as manual reset, etc.
■The diagram above shows how a ProcessorPM-POWR605 is used in a typical application. It controls power to the microprocessor system, generates the CPU reset and monitors critical power supply voltages, generating interrupts whenever faults are detected. It also provides a watchdog timer function to detect CPU operating and bus timeout errors.
■The ProcessorPM-POWR605 incorporates a 16-macro-cell CPLD. Figure 1 shows the analog input compara-tors and digital inputs used as inputs to the CPLD array. The digital output pins providing the external control sig-nals are driven by the CPLD. Four independently pro-grammable timers also interface with the CPLD and can create delays and time-outs ranging from 32μs to 2 sec-onds. The CPLD is programmed using LogiBuilder™, an easy-to-learn language integrated into the PAC-Designer® software. Control sequences are written to monitor the status of any of the analog input channel comparators or the digital inputs.
●Features:
■Precision Programmable Threshold Monitors, Threshold Accuracy 0.7%
▲ Simultaneously monitors up to six power supplies
▲ Programmable analog trip points (1% step size;192 steps)
▲ Programmable glitch filter
▲ Power-off detection (75mV)
■Embedded Programmable Timers
▲ Four independent timers
▲ 32μs to 2 second intervals for timing sequences
■Embedded PLD for Logical Control
▲ Rugged 16-macrocell CPLD architecture
▲ 81 product terms / 28 inputs
▲ Implements state machines and combinatorial functions
■Power-Down Mode I-CC < 10μA
■Digital I/O
▲ Two dedicated digital inputs
▲ Five programmable digital I/O pins
■Wide Supply Range (2.64V to 3.96V)
▲ In-system programmable through JTAG
▲ Industrial temperature range: -40°C to +85°C
▲ 24-pin QFN package, lead-free option
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general-purpose power-supply monitor 、 reset genera-tor 、 watchdog timer 、 In-System Programmable Power Supply Supervisor |
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Datasheet |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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February 2012 |
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Version 01.3 |
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DS1034_01.3 |
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2.9 MB |
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