SL2309 Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer (ZDB)

2022-04-19

The SL2309 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to nine (9) clock outputs from one (1) reference input clock, for high speed clock distribution applications.
The product has an on-chip PLL which locks to the input clock at CLKIN and receives its feedback internally from the CLKOUT pin.
The SL2309 has two (2) clock driver banks each with four (4) clock outputs. These outputs are controlled by two (2) select input pins S1 and S2. When only four (4) outputs are needed, four (4) bank-B output clock buffers can be tri-stated to reduce power dissipation and jitter. The select inputs can also be used to tri-state both banks A and B or drive them directly from the input bypassing the PLL and making the product behave like a Non-Zero Delay Fanout Buffer (NZDB).
The high-drive(-1H)version operates up to 140MHz and low drive(-1)version operates up to 100MHzat 3.3V.
●Benefits
■Up to nine (9) distribution of input clock
■Standard and High-Drive levels to control impedance level, frequency range and EMI
■Low power dissipation, jitter and skew
■Low cost
●Key Features
■10 to 140MHz operating frequency range
■Low output clock jitter:
▲140ps-maxcycle-to-cycle jitter
■Low output-to-output skew: 150 ps-max
■Low product-to-product skew: 400 ps-max
■3.3 V power supply range
■Low power dissipation:
▲26mA-maxat 66 MHz
▲44mA –max at 133MHz
■One input drives 9 outputs organized as 4+4+1
■Select mode to bypass PLL or tri-state outputs
■Spread Thru™PLL that allows use of SSCG
■Standard and High-Drive options
■Available in 16-pin SOIC and TSSOP packages
■Available in Commercial and Industrial grades.

Silicon Labs

SL2309SL2309BZC-1HSL2309BZC-1HTSL2309BZI-1HSL2309BZI-1HTSL2309BSC-1SL2309BSC-1TSL2309BSC-1HSL2309BSC-1HTSL2309BSI-1SL2309BSI-1TSL2309BSI-1HSL2309BSI-1HTSL2309ZC-1[4]SL2309ZC-1T[4]SL2309ZC-1H[4]SL2309ZC-1HT[4]SL2309ZI-1[4]SL2309ZI-1T[4]SL2309ZI-1H[4]SL2309ZI-1HT[4]SL2309SC-1[4]SL2309SC-1T[1]SL2309SC-1H[4]SL2309SC-1HT[4]SL2309SI-A[4]SL2309SI-1T[4]SL2309SI-1H[4]SL2309SI-1HT[4]SL2309SC-1T[4]SL2309SI-1[4]

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Part#

Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer

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Datasheet

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16-pin TSSOP;16-pin SOIC

English Chinese Chinese and English Japanese

May 12, 2008

Rev 2.0

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