20-bit registered driver with inverted register enable (3-State)
●The 74ALVC16836A is a 20-bit universal bus driver. Data flow is controlled by active low output enable (OE), active low latch enable(LE) and clock inputs (CP).
●When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the A-data is stored in the latch/flip-flop.
●When OE is LOW the outputs are active. When OE is HIGH, the outputs go to the high impedance OFF–state. Operation of the OE input does not affect the state of the latch/flip-flop.
●To ensure the high-impedance state during power up or power down, OE should be tied to V-CC through a pull up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
●Features:
■Wide supply voltage range of 1.2 V to 3.6 V
■Complies with JEDEC standard no. 8-1A.
■CMOS low power consumption
■Direct interface with TTL levels
■Current drive ± 24 mA at 3.0 V
■MULTIBYTE™ flow-through standard pin-out architecture
■Low inductance multiple V-CC and GND pins for minimum noise and ground bounce
■Output drive capability 50 Ω transmission lines @ 85°C
■Input diodes to accommodate strong drivers
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Datasheet |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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2000 Mar 14 |
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9397-750-06959 |
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437 KB |
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