TD4GBDDR372 4GByte, DDR3, 512M x 72 Single Channel Memory Module
■Wide Word DD3 SDRAM Module Configuration
▲64Meg x 72 x 8 banks x 1 Channels
▲VDD=VDDQ=1.35V
▲Backward compatable to 1.5V applications
▲Center-terminated I/O
▲Pin-out supports Clam Shell layout on opposite sides of PC board
▲15mm x 20mm x 1.9 mm Package with 399 balls
▲Matrix ball pitch: 0.8mm Space saving footprint
■Thermally enhanced, Impedance matched, integrated packaging
■Differential, i-directional data strobe
■8n-bit prefetch architecture
■8 internal banks (per word, 4 words integrated in package(Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals.
■Programmable CAS (READ) latency (CL): 9, 11 and 13
■CAS (WRITE) latency (CWL): 9, 11, and 13
■Fixed burst length (BL) of 8 and burst chop (BC) of 4
■Selectable BC4 or BL8 on-the-fly (OTF)
■Self/Auto Refresh modes
■Temperature Compensated Refresh
■Operating Temperature Range (ambient temp=TA)
▲Industrial: -40°C to 85°C supporting
■Self & Auto Refresh
■Clocking frequencies: 800, 900 MHz
■Transfer Rates: 1600, 1866 Mbps
■Write leveling
■Output Driver Calibration
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Datasheet |
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Please see the document for details |
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PBGA |
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English Chinese Chinese and English Japanese |
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11/29/2017 |
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Rev. 1 |
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3.9 MB |
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