GS8662Q08/09/18/36BD-300M 72Mb SigmaQuad-II™ Burst of 2 SRAM
●The GS8662Q08/09/18/36BD are built in compliance with the SigmaQuad-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. The GS8662Q08/09/18/36BD SigmaQuad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
■Features
●Military Temperature Range
●Simultaneous Read and Write SigmaDDR™ Interface
●JEDEC-standard pinout and package
●Double Data Rate interface
●Byte Write controls sampled at data-in time
●Burst of 2 Read and Write
●1.8 V +100/–100 mV core power supply
●1.5 V or 1.8 V HSTL Interface
●Pipelined read operation
●Fully coherent read and write pipelines
●ZQ pin for programmable output drive strength
●IEEE 1149.1 JTAG-compliant Boundary Scan
●Pin-compatible with present 144 Mb devices
●165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
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GS8662Q08BD 、 GS8662Q09BD 、 GS8662Q18BD 、 GS8662Q36BD 、 GS8662Q36BD-300MT 、 GS8662Q36BD-300M 、 GS8662Q18BD-300M 、 GS8662Q09BD-300M 、 GS8662Q08BD-300M |
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Datasheet |
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Please see the document for details |
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BGA;FPBGA |
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English Chinese Chinese and English Japanese |
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10/2012 |
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Rev: 1.00 |
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8662QxxB-300M_r1 |
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507 KB |
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