GSI Technology Product Listing
2022-03-23
●INTRODUCTION
■The Bandwidth Engine architecture is a highly parallel, multi-bank, multi-ported 1T-SRAM based memory array coupled with a high efficiency serial interface and on-board functionality, delivering intelligent scheduled access in addition to the highest memory transaction rate, table read rate and data throughput of any single chip device.
●FEATURES
■1152Mb 1T-SRAM® memory array architecture
■3.2 ns core cycle time
■Low latency SerDes technology
■4, 8 or 16 serial transceivers (TX/RX)
■OIF CEI-11G-SR and CEI-28G-VSR compatible
■Tuned for low-power transmission up to 20 cm
■Open GigaChip® Interface delivers bandwidth, efficiency andreliability
■Low latency protocol
■Reliability with scrambling, CRC and error recoverymechanisms
■Intelligent Error Management and Bit Safe® Technology
■High reliability—1T-SRAM soft error immunity
■Advanced debugging and evaluation capabilities with IC Spotlight software
●INTRODUCTION
■The Bandwidth Engine family of ICs enables a new way of looking at network packet processing with the most efficient serial interface and a highly parallel memory array. The intelligence and error resilience in the Array Manager, and reliable transport interface removes complexity from the host device and ensures end-to-end data integrity. The Bandwidth Engine family of ICs was designed and built with enterprise and carrier markets in mind.
●FEATURES
■576Mb 1T-SRAM® memory array architecture
■2.56 ns core cycle time, < 16 ns read latency
■Low latency SerDes technology up to 15.625Gbps
■Up to 16 serial transceivers (TX/RX)
■OIF CEI-11G-SR and XFI compatible interface
■Tuned for low power transmission up to 20 cm
■High performance GigaChip® Interface
■High efficiency format utilizing scrambling
■CRC error detection and automatic recovery
■Intelligent Error Management and Bit Safe™ Technology
■High reliability—1T-SRAM soft error immunity
■The Bandwidth Engine architecture is a highly parallel, multi-bank, multi-ported 1T-SRAM based memory array coupled with a high efficiency serial interface and on-board functionality, delivering intelligent scheduled access in addition to the highest memory transaction rate, table read rate and data throughput of any single chip device.
●FEATURES
■1152Mb 1T-SRAM® memory array architecture
■3.2 ns core cycle time
■Low latency SerDes technology
■4, 8 or 16 serial transceivers (TX/RX)
■OIF CEI-11G-SR and CEI-28G-VSR compatible
■Tuned for low-power transmission up to 20 cm
■Open GigaChip® Interface delivers bandwidth, efficiency andreliability
■Low latency protocol
■Reliability with scrambling, CRC and error recoverymechanisms
■Intelligent Error Management and Bit Safe® Technology
■High reliability—1T-SRAM soft error immunity
■Advanced debugging and evaluation capabilities with IC Spotlight software
●INTRODUCTION
■The Bandwidth Engine family of ICs enables a new way of looking at network packet processing with the most efficient serial interface and a highly parallel memory array. The intelligence and error resilience in the Array Manager, and reliable transport interface removes complexity from the host device and ensures end-to-end data integrity. The Bandwidth Engine family of ICs was designed and built with enterprise and carrier markets in mind.
●FEATURES
■576Mb 1T-SRAM® memory array architecture
■2.56 ns core cycle time, < 16 ns read latency
■Low latency SerDes technology up to 15.625Gbps
■Up to 16 serial transceivers (TX/RX)
■OIF CEI-11G-SR and XFI compatible interface
■Tuned for low power transmission up to 20 cm
■High performance GigaChip® Interface
■High efficiency format utilizing scrambling
■CRC error detection and automatic recovery
■Intelligent Error Management and Bit Safe™ Technology
■High reliability—1T-SRAM soft error immunity
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