GS8180QV18/36BD-200/167 18Mb Burst of 2 SigmaQuad SRAM
●GS8180QV18/36B are built in compliance with the SigmaQuad SRAM pinout standard for Separate I/O synchronous SRAMs. They are18,874,368-bit (18Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
●SigmaQuad SRAMs are offered in a number of configurations. Some emulate and enhance other synchronous separate I/O SRAMs. A higher performance SDR (Single Data Rate) Burst of 2 version is also offered. The logical differences between the protocols employed by these RAMs hinge mainly on various combinations of address bursting, output data registering, and write cueing. Along with the Common I/O family of SigmaRAMs, the SigmaQuad family of SRAMs allows a user to implement the interface protocol best suited to the task at hand.
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GS8180QV18BD 、 GS8180QV36BD 、 GS8180QV36B 、 GS8180QV18B 、 GS8180QV18BD-200 、 GS8180QV18BD-167 、 GS8180QV36BD-200 、 GS8180QV36BD-167 、 GS8180QV18BD-200I 、 GS8180QV18BD-167I 、 GS8180QV36BD-200I 、 GS8180QV36BD-167I 、 GS8180QV18BGD-200 、 GS8180QV18BGD-167 、 GS8180QV36BGD-200 、 GS8180QV36BGD-167 、 GS8180QV18BGD-200I 、 GS8180QV18BGD-167I 、 GS8180QV36BGD-200I 、 GS8180QV36BGD-167I |
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Datasheet |
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Please see the document for details |
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BGA;FPBGA |
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English Chinese Chinese and English Japanese |
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11/2011 |
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Rev: 1.02b |
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8180QVxxBD_r1.02 |
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408 KB |
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